Low Density Parity Check (LDPC) codes that were introduced in the nineteen-sixties have received a great deal of attention in recent years for an ability to achieve performance close to the Shannon limit Additionally, the structure of LDPC codes is suitable for fast and efficient parallel decoding. Consequently, currently active telecommunication standards, such as IEEE 802.16e, WiGig, IEEE 802.15.3c, and DVB-S2, utilize LDPC block codes in their physical layer error control coding scheme.
In wireless communication systems, the baseband modem power consumption is significantly affected by the channel decoder complexity, especially when LDPC codes are used. The LDPC codes that are used in commercial standards are block codes, which means that the LDPC encodes each non-overlapping block of bits independently. The block size affects the code error rate as well as the processing latency. Increasing the block size, leads to a decrease in the bit-error-rate (BER) of the code. A larger block size also increases the latency because block codes are non-instantaneous and fragments of the encoded and decoded block cannot be output before completely processing all the bits in the block. In many wireless standards multiple block sizes are defined to provide flexibility to satisfy different application latency and error rate requirements. However, the plurality of block sizes, in certain standards, increases the encoding and decoding complexity of LDPC block code in hardware (HW), leading to an increase in the overall power consumption of the baseband modem for a given Signal-to-Noise Ratio (SNR), BER, and data rate. The most common LDPC block decoding techniques currently used such as Belief Propagation (BP) are iterative-based which requires multiple decoding iterations (i.e., 8 or 16 iterations) to correctly decode the bits at a low SNR. The overall LDPC decoder HW complexity increases linearly with iterations, while also reducing the SNR required to satisfy the desired BER. In addition, the matrix-based structure of the LDPC block codes causes any attempt to increase the LDPC block decoder processing rate by using a technique such as pipelining will result in no decrease or even to increase of the overall LDPC code power consumption as a result of the extra registers that are required. Time-varying LDPC convolutional codes are introduced by A. Jiménez Feltström and K. S. Zigangirov, in “Time-varying periodic convolutional codes with low-density parity-check matrix,” IEEE Transactions on IT, vol. IT-45, no. 6, pp. 2181-2191, September 1999 (hereinafter “REF9”) and enhanced by A. E. Pusane, R. Smarandache, P. O. Vontobel, D. J. Costello, Jr., in “Deriving Good LDPC Convolutional Codes from LDPC Block Codes,” IEEE Transactions on IT, Vol. 57, No. 2, pp. 835-857, February 2011 (hereinafter “REF22”) to offer lower BER performance. However, the LDPC convolutional codes still require iterative belief-propagation based (BP-based) decoding that results in large latency, high hardware complexity and power consumption.